The present invention relates to a method and apparatus for controlling both active and standby power in domino circuits.
Complementary metal oxide semiconductor (CMOS) compound domino logic (CDL) circuits or domino circuits are known. CMOS domino circuits provide a logical function, such as an OR function or an AND function, providing a logical output signal responsive to a plurality of input signals.
High speed CMOS circuits often employ a domino circuit technique that utilizes pre-charging to improve the gate speeds of the transistors. Many domino circuits include a P-channel field effect transistor (PFET) that is clocked to precharge an intermediate node causing the output to go to a predetermined logic state. Circuit nodes are pre-charged during each clock cycle to a certain level.
While dynamic circuits offer a significant area and performance advantage over other circuit styles, one of their major disadvantages is potentially higher power dissipation when compared to static CMOS circuits. This is because a dynamic circuit relies on the clock to precharge the circuit, and then conditionally discharges depending upon the states of the inputs to the circuit.
FIG. 1 shows the topology of one type of dynamic circuit, an unfooted domino logic gate. As shown in FIG. 1, a precharge PFET device is gated by CLOCK to precharge an intermediate node coupled to an output inverter. A plurality of input signals is applied to an N-channel field effect transistor (NFET) network connected to the intermediate node and the output inverter that provides a logical output signal responsive to the plurality of input signals. A feedback or half-latch device is connected to the intermediate node having a gate input connected to the output of the output inverter. A domino logic gate with a footer includes an additional NFET, gated by CLOCK, between the NFET network and ground.
Like most dynamic circuits, domino gates can switch both high and low up to once per cycle. For example, in a simple dynamic two input wide OR function, the precharge node will be driven to VDD through the precharge device and then, when the clock is low, if either input goes high the precharge node will discharge and the output will go high. This will happen each cycle even if the inputs do not change. As long as either input is high, in the case of an OR gate, when the clock is low, the precharge and output nodes will make a transition. This results in higher power dissipation than, for example, a static CMOS OR gate that does not transition as long as the inputs are stable. In many cases the output of the dynamic circuit is not even required in a particular clock cycle, but it transitions, wasting power, nonetheless.
In addition, since dynamic circuits require a clock to enable their precharge, the clock circuitry must dissipate power each cycle charging and discharging clocked transistors, even if the logic implemented in the dynamic circuit is not required or involved in a particular cycle. For example, a dynamic rotator circuit contains many precharge and evaluate transistors which are connected to the clock distribution network and are switched every cycle, but instructions which use the rotator circuit comprises a tiny fraction of the instruction mix in a typical workload.
Traditional approaches to minimizing this wasteful switching activity include gating clocks so that when the output of the circuit is not required, or can be generated from some other mechanism; the dynamic circuit is placed in standby mode. The intent of standby mode is to limit or eliminate the switching activity that occurs in a dynamic circuit when it is not being used.
Unfortunately, the traditional approaches do nothing to reduce leakage current. Leakage current occurs in transistors that are off. For example, leakage current occurs in an NFET that is off the gate of the NFET is below a threshold voltage (VT) of the NFET. Leakage current is becoming an increasingly large fraction of the total power dissipation in high performance circuits. For example, in a processor designed in a 0.18 xcexcm silicon-on-insulator (SOI) technology, leakage power typically accounts for approximately 30% of the total power dissipation in product that has been fabricated with short channel lengths. The regions of the substrate that receive dopants on opposite sides of the gate conductor are referred to as junction regions and the distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions become less than the physical channel length and is referred to as the effective channel length (LEFF). In high density designs, the physical channel length and the effective channel length (LEFF) are typically short.
Leakage current can be controlled by the use of transistors with longer channel lengths (LEFF) and/or higher threshold voltage (VT) than the minimum that are allowed by a technology. Unfortunately, high VT or long LEFF transistors have less drive and result in slower circuits. Using high VT and long LEFF transistors to control standby or leakage current can be counterproductive since the designer may need to use larger (greater width) transistors to compensate for the reduced performance of the high VT long LEFF devices, the net result of which is a higher active power.
Another approach is to use low leakage header device or footer device that serve to block the path from VDD or ground respectively but these devices tend to place impedance in the critical path of the circuit and require a large area to implement.
A need exists for an effective mechanism for controlling both active and standby power in domino circuits.
A principal object of the present invention is to provide an improved method and apparatus for controlling both active and standby power in domino circuits. Other important objects of the present invention are to provide such a method and apparatus for controlling both active and standby power in domino circuits substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for controlling both active and standby power in a domino circuit. A precharge device is connected to an intermediate precharge node and is arranged to minimize leakage current through the precharge device when deactivated. An input transistor network receiving a plurality of data inputs is connected to the intermediate precharge node. An output inverter is connected to the intermediate precharge node and includes a pair of transistors. A predefined transistor of the pair of transistors is arranged to minimize leakage current through the output inverter. A standby control signal is asserted for a standby mode of the domino circuit and is unasserted for an active mode of the domino circuit. The standby control signal and a clock signal are combined to provide a combined standby clock signal. The combined standby clock signal controls the precharge device. The precharge device is deactivated responsive to the standby control signal being asserted. A standby discharge device is connected to the intermediate precharge node and controlled by the standby control signal. The standby discharge device is activated to discharge the intermediate precharge node responsive to the standby control signal being asserted.
In accordance with features of the invention, a field effect transistor having either a predefined higher threshold voltage (VT) or a longer design channel length is used for both the precharge device and the predefined transistor of the pair of transistors to minimize leakage current in the domino circuit. The standby discharge device is a small N-channel field effect transistor (NFET) connected between the intermediate precharge node and ground.